Introduction

Here you will find a collection of some Avalon Components which are used in the projects.

Altera Qsys: If you want to use one of my Qsys component in your project, copy the ZIP file of the component in the IP folder of your project and expand the ZIP file. After refreshing Qsys, the new component should be available in the component library. For more information about Qsys and components, please take a look at the Altera document Creating a System With Qsys.

Ethernet DM9000E Interface (Qsys)

The Ethernet DM9000E Interface is a 16 bit Avalon-MM Slave which is inspired by the Terasic example and coded in VHDL. The data sheet of the DM9000E can be found here.

Frequency: Tested with a 140 MHz bus clock.

Download : dm9000e_v12_20120815.zip

7-segment display, DE1/DE2 (Qsys)

This is the component for the 7-segment display of the Altera DE1/DE2 board. It is inspired by the Terasic example and coded in VHDL. My component here has a read port too. Please take a look in the user manual of the DE1/DE2 board for the data sheet.

Frequency: Tested with a 100 MHz bus clock.

Download : seg7_lut_8_v12_20120815.zip

IS61LV25616AL-10 SRAM (Qsys)

This is the IS61LV25616AL-10 SRAM interface which is inspired by the Terasic example and coded in VHDL.The data sheet of the SRAM can be found here.

Frequency: Tested with a 100 MHz bus clock.

Download : is61lv25616al_10_v11_20120805.zip

Software SPI Master (Qsys)

This component is a very simple PIO implementation. The SPI interface will be used for the SD Card of an Altera DE1 board. A SD write rate of about 75 kBytes/sec was reached with a Nios II/e running at 100 MHz.

Frequency: Tested with a 100 MHz bus clock.

Download : pio_spi_v11_20120822.zip

Hardware SPI Master (Qsys)

This SPI master based on the example from Lothar Miller which can be found here, many thanks to Lothar. I have added some functionality to change the bit rate and width at runtime. The SPI interface will be used for the SD Card of an Altera DE1 board. A SD write/read rate of more than 900 kBytes/sec was reached with a Nios II/e running at 100 MHz.

Frequency: Tested with a 100 MHz bus clock.

Download : spi_master_v13_20130817.zip